1. Technical Field
The present invention relates to a semiconductor device fabricated using a chemical-mechanical polishing (CMP) method, the semiconductor device being provided with shallow trench isolation (STI) and wire structures. The present invention also relates to a layout design method of such semiconductor device and a layout design device that uses the method.
2. Related Art
Commonly introduced elements and wiring structures of semiconductor devices have thin-film multilayer structures, in order to make semiconductor devices more highly integrated and greatly reduced in scale. The manufacturing of these elements involves a CMP method for planarizing deposited surfaces, and the flatness of the substrate polished by this method depends on the layout of the wirings. In order to ensure the flatness, a suggested method includes the forming of dummy wirings (refer to JP-A-2003-45876 for an example). In order to ensure the flatness in a semiconductor substrate that has element isolation regions formed with STI, a suggested method includes forming dummy activation areas in an STI structure (refer to JP-A-2004-356316 for an example).
As described, the flatness in the CMP polishing is ensured by patterning dummy wirings and dummy activation areas.
These cases, however, may involve occurrences of phenomenon where static electricity is transmitted to internal circuits.
The cause of the above is determined to be an involuntarily formed conductive channel created by patterning the dummy activation areas, causing the static electricity flown in through the input-output pad to be transmitted to the internal circuits through the dummy activation areas.